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Download The following .zip archive contains all the source files, pc support tools and MPLAB development environment stuff. It also contains a precompiled binary .hex file for downloading to the PIC: Download FFC.ZIP Check back for regular updates. Software architecture Modules Everything in the code is modularised with each .asm source file typically containing one module. Some contain more than this if really small or so large as to need splitting over two modules. The modules are all linked together according to the linker file ffc.lkr. This says which of the four PIC program memory banks the modules are to be located in. It also positions the lookup tables ensuring they don't cross any 256 byte boundaries. From time to time it is necessary to rejuggle this as code grows. The best way to do this is to do a full build of all objects and examine the output .lst files for the section lengths. Scheduler and Interrupts Everything, as the name implies, revolves around main.asm. This calls out to all the modules in turn and also contains interrupt handling routines. The interrupts keep track of time and related functions and set flags accordingly. These are checked and cleared by the non-interrupt code which then takes the appropriate action. The routines called by the scheduler are only called if they need to be. For some routines this is every time, though they may not have anything to do, whereas others need only be called if something is set. The bulk of the processing takes place between main.asm and measure.asm. Tasks are scheduled according to a tick count derived from the adc readings. There are 25 adc reads in a second and the tasks are spread evenly across this time to maintain even processor loading. This can be clearly seen at the top of the measure.asm file. Engineering handler The one exception to the nice even processor loading is the engineering handler. As it's only used for development, calibration, or barograph downloads there is no need to complicate the normal situation with this consideration. The commands provided are as follows: RD xx yy where xx and yy is EEPROM location WR xx yy zz writes zz to xx yy SEND x y where x is barograph 1 or 2 and y is trace from 0 on ... DUMP dump entire ram contents to UART RESET resets FFC ADC x y Read ADC (x=0 internal, x=1 external, y=channel) The physical interface settings are 19200 baud 8 data bits, no parity and 1 stop bit (8N1). It is this interface that the PC based applications use to talk to the FFC. Back to top ...